1. Field of the Invention
The present invention relates to a semiconductor device in which a plurality of unit components is arranged, and a control method and device for driving the unit components. In particular, the present invention relates to a technology to reduce power consumption and to increase the dynamic range of a physical-quantity-distribution-sensing semiconductor device, such as a solid-state imaging device. In the physical-quantity-distribution-sensing semiconductor devices, for example, unit components, such as unit pixels, that are sensitive to externally input electromagnetic waves, such as light and radiation, are arranged in a matrix, and the physical quantity distribution is converted to electrical signals to be read out.
2. Description of the Related Art
Physical-quantity-distribution-sensing semiconductor devices, in which unit components, such as unit pixels, that are sensitive to externally input electromagnetic waves, such as light and radiation, are arranged in a line or a matrix, are being widely used in various fields. For example, in the field of imaging devices, solid-state imaging devices having charge coupled devices (CCDs), metal oxide semiconductors (MOSs), or complementary metal-oxide semiconductors (CMOSs), are used, all of which sense light as one of the physical quantities. In such semiconductor devices, unit components (unit pixels in the case of solid-state imaging devices) read out electrical signals converted from the physical quantity distribution.
In addition, the solid-state imaging devices include an active pixel sensor solid-state imaging device having pixels of active pixel sensor (APS, also referred to as a gain cell) structure. In each APS pixel, a pixel signal generation unit includes an amplifying driving transistor for generating a pixel signal in accordance with signal charge generated by a capacitance generation unit. For example, most CMOS solid-state imaging devices have such a structure. In these active pixel sensor solid-state imaging devices, to read out a pixel signal, a pixel unit having a plurality of unit pixels is controlled by an address so that any unit pixel can be selected to read out the signal therefrom. That is, the active pixel sensor solid-state imaging device is an example of an address-controlled solid-state imaging device.
For example, in the active pixel sensor, which is one type of X-Y address type solid-state imaging sensor having unit pixels in a matrix, a pixel is composed of an active element having a MOS structure (MOS transistor) to provide the pixel itself with an amplifying function. That is, the active pixel sensor reads out signal charge (photoelectrons) accumulated in a photodiode (photoelectric transducer) and amplified by the active element as image information.
In this X-Y address type solid-state imaging sensor, for example, a plurality of pixel transistors is arranged in a two-dimensional matrix to form a pixel unit. Accumulation of signal charges in accordance with incident light starts line by line or pixel by pixel. A current or voltage signal based on the accumulated signal charge is sequentially read out from each pixel by specifying the address.
Unit Pixel Structure; 4-TR Type
In general, in a complementary metal-oxide semiconductor (CMOS) sensor, a structure of a unit pixel is complicated compared to that of a charge coupled device (CCD) sensor because of reducing the noise. For example, as shown in FIG. 1A, a general-purpose CMOS sensor includes a floating diffusion amp (FDA), which is a diffusion layer having a parasitic capacitance, and four transistors in a unit pixel 3. This structure is well known and is referred to as a 4-transistor pixel structure (hereinafter also referred to as a 4TR-structure).
In this 4TR-structure, a floating diffusion 38, which is an example of a charge accumulation unit, is connected to a gate of an amplifying transistor 42, which is an example of a signal generation unit. Accordingly, the amplifying transistor 42 outputs a signal (voltage signal in this case) in accordance with a potential of the floating diffusion 38 (hereinafter also referred to as an FD potential) to a vertical signal line 53, which is an example of an output signal line, via a pixel line 51. A reset transistor 36 resets the floating diffusion 38.
A transfer gate transistor (readout selection transistor) 34 functioning as a charge transfer unit transfers signal charge generated by a charge generation unit 32 to the floating diffusion 38. A plurality of pixels is connected to the vertical signal line 53. In order to select a pixel, a vertical selection transistor 40 in a pixel to be selected is turned on. This allows only the selected pixel to be connected to the vertical signal line 53, and therefore, a signal of the selected pixel is output to the vertical signal line 53.
Thus, the unit pixel 3 generally includes a photoelectric transducer, for example, a photodiode (PD), and four transistors, one of which is the vertical selection transistor 40 for selecting a pixel. The unit pixel 3 of most current CMOS sensors has the selection transistor. Therefore, CMOS sensors have a disadvantage in terms of increasing the resolution compared to CCD sensors.
Unit Pixel Structure; 3-TR Type
On the other hand, a 3-transistor pixel structure (hereinafter also referred to as a 3TR-structure) is proposed to reduce the number of elements while maintaining the performance. As shown in FIG. 1B, to reduce a pixel size by reducing spaces occupied by transistors in the unit pixel 3, the unit pixel 3 includes a photoelectric transducer, for example, a photodiode (PD), and three transistors (refer to, for example, Japanese Patent No. 2708455). Hereinafter, this patent document is referred to as Patent Document 1.
Each unit pixel 3 of a 3TR-structure includes a charge generation unit 32, such as a photodiode, which receives light and photoelectrically converts it to generate signal charge; an amplifying transistor 42, which is connected to a vertical drain line (DRN) 57 and amplifies a signal voltage corresponding to the signal charge generated by the charge generation unit 32; and a reset transistor 36 for resetting the charge generation unit 32. Additionally, a readout selection transistor (transfer gate unit) 34 is disposed between the charge generation unit 32 and a gate of an amplifying transistor 42. The readout selection transistor 34 is scanned by a vertical shift register in a vertical scanning circuit (not shown) via a transfer gate wire (TRG) 55. That is, the unit pixel 3 of a 3TR-structure includes three transistors for transferring, resetting, and amplifying, in addition to the charge generation unit 32.
A gate of the amplifying transistor 42 and a source of the reset transistor 36 are connected to the charge generation unit 32 via the transfer gate transistor (readout selection transistor) 34. A drain of the reset transistor 36 and a drain of the amplifying transistor 42 are connected to the drain line. A source of the amplifying transistor 42 is connected to the vertical signal line 53. The transfer gate transistor 34 is driven by a transfer driving buffer 150 via the transfer gate wire (TRG) 55. The reset transistor 36 is driven by a reset driving buffer 152 via a reset gate wire (RST) 56.
Both the transfer driving buffer 150 and the reset driving buffer 152 operate by two values, the reference voltage 0 V and a power supply voltage. In particular, in a known unit pixel of this type, a low level voltage applied to the gate of the transfer gate transistor 34 is 0 V.
Pixels in the same horizontal row are connected to three signal lines, namely, the transfer gate wire (TRG) 55, the reset gate wire (RST) 56, and a vertical drain line (DRN) 57. Pixels in the same vertical column are connected to a common vertical signal line (readout signal line) 53. The amplifying transistor 42 is connected to each vertical signal line 53, which is connected to a corresponding load transistor unit (not shown). When a signal is read out, a MOS load transistor connected to each amplifying transistor 42 continuously supplies a predetermined constant current to the vertical signal line 53.
Each vertical signal line 53 is connected to a column circuit (not shown), which removes noise by using a correlated double sampling (CDS). The processed pixel signal is read out from the column circuit under the control of a horizontal scanning circuit (not shown). The pixel signal is then delivered to an amplifier circuit (an output amplifier) and is externally output.
A vertical scanning circuit (not shown) drives the transfer gate wire (TRG) 55, the reset gate wire (RST) 56, and the vertical drain line (DRN) 57 at an appropriate timing to control pixels in the same horizontal row. During readout time, the horizontal scanning circuit sequentially inputs signals to CDS processing units to turn them on. Thus, signals read out from the respective vertical signal line 53 are sequentially delivered to the output amplifier.
As in the 4TR-structure, in the unit pixel 3 of the 3TR-structure, a floating diffusion 38 is connected to a gate of an amplifying transistor 42. Accordingly, the amplifying transistor 42 outputs a signal in accordance with a potential of the floating diffusion 38 to the vertical signal line 53.
The reset gate wire (RST) 56 connected to a gate of the reset transistor 36 extends in the row (horizontal) direction, and the vertical drain line (DRN) 57 connected to a drain of the reset transistor 36 is common to all the pixels. The vertical drain line (DRN) 57 is driven by a drain driving buffer 140 (hereinafter referred to as a DRN driving buffer). The reset transistor 36 is driven by the reset driving buffer 152 to control a potential of the floating diffusion 38.
In Patent Document 1, the vertical drain line (DRN) 57 for one row is separated from that for another row. However, since the vertical drain line (DRN) 57 must allow current signals of pixels in one column to flow thereon, the vertical drain line (DRN) 57 is actually common to all rows.
Signal charge generated by the charge generation unit (photoelectric transducer) 32 is transferred to the floating diffusion 38 by the transfer gate transistor 34.
Unlike the 4TR-structure, the unit pixel 3 of a 3TR-structure does not have the vertical selection transistor 40 to be connected to the amplifying transistor 42 in series. Among a plurality of pixels connected to the vertical signal line 53, a pixel is selected not by the vertical selection transistor 40 but by controlling the FD potential.
Thus, level control of the vertical drain line (DRN) 57 functions as selection of a pixel. The vertical drain line (DRN) 57 is effectively used as a pixel selection line (SEL), which has the same function as the vertical selection line (SEL) 52 in the first example. Additionally, a pulse signal on the vertical drain line (DRN) 57, which controls both drains of the reset transistor 36 and the amplifying transistor 42, has the same function as the selection pulse SEL in the first example. Hereinafter, the pulse signal on the vertical drain line (DRN) 57 is referred to as a DRN control pulse SEL.
For example, the FD potential is usually forced to a low level (Low) by switching the vertical drain line (DRN) 57 to a low level. To select a pixel, the FD potential of the selected pixel is forced to a high level (High) by switching the vertical drain line (DRN) 57 to a high level and switching the reset transistors 36 in the selected row in order to output a signal of the selected pixel to the vertical signal line 53. Thereafter, the FD potential of the selected pixel is returned to a low level by switching the vertical drain line (DRN) 57 to a low level. This operation is performed for all the pixels in the selected row at the same time.
Thus, in order to control the FD potential, the following operations must be performed:    1) To turn the FD potential of the selected row to a high level, the vertical drain line (DRN) 57 is switched to a high level and the FD potential becomes a high level via the reset transistor 36 for the selected row.    2) To return the FD potential of the selected row to a low level, the vertical drain line (DRN) 57 is switched to a low level and the FD potential becomes a low level via the reset transistor 36 for the selected row.
FIG. 2 is an example of a timing chart of driving pulses for driving the unit pixel 3 of the 3-TR structure. By controlling the transfer gate wire (TRG) 55, the reset gate wire (RST) 56, the vertical drain line (DRN) 57 common to the pixels, the voltage of the floating diffusion 38 varies, and therefore, the voltage of the vertical signal line 53 also varies.
For example, the DRN driving buffer 140 applies a drain driving pulse DRN (high level) to the vertical drain line (DRN) 57 to switch the vertical drain line (DRN) 57 to a high level. While the vertical drain line (DRN) 57 is at a power supply voltage (high) level, a reset pulse RST (high level) is applied to the reset transistor 36 to raise the reset gate wire (RST) 56 to a high level (t1). Thus, the floating diffusion 38 is connected to the power supply voltage. Thereafter, when the reset gate wire (RST) 56 falls to a low level (t2), the voltage of the floating diffusion 38 falls due to a capacity coupling C1 between a gate (reset gate) of the reset transistor 36 and the floating diffusion 38.
This change appears on the vertical signal line 53 through the amplifying transistor 42. Therefore, a voltage of the vertical signal line 53 falls. Then, the voltage of the floating diffusion 38 further falls due to a capacity coupling C2 between the vertical signal line 53 and a gate of the amplifying transistor 42.
Due to these effects, the voltage of the floating diffusion 38 (FD voltage) decreases to lower than the power supply voltage (from t2 to t3). A downstream circuit connected to the vertical signal line 53 receives the voltage of the vertical signal line 53 (reset level), which corresponds to this FD voltage.
Subsequently, when a transfer gate pulse TRG (high level) is applied to the transfer gate transistor 34 (from t3 to t4), the charge generation unit 32 transfers signal charge (photoelectrons) to the floating diffusion 38 to decrease the voltage of the floating diffusion 38, and therefore, the voltage of the vertical signal line 53 also decreases with the decrease of the voltage of the floating diffusion 38 (from t4 to t5). The downstream circuit also receives this voltage of the vertical signal line 53 (signal level).
Thereafter, when the vertical drain line 57 is switched to a low level and a reset pulse RST is applied to the reset transistor 36 (from t5 to t6), the floating diffusion 38 returns to a low level (after t5). The downstream circuit calculates the difference between the reset level and the signal level to output it as a pixel signal.
However, this type of driving decreases the voltage of the floating diffusion 38 after resetting due to the capacity couplings C1 and C2 (from t2 to t3). Accordingly, a high power supply voltage is required to compensate for the decrease, that is, lower levels of voltage cannot be used, and therefore, low power consumption and wide dynamic range cannot be provided, which are problems.
A pixel unit 3 of the 4-TR structure that has the vertical selection transistor 40 in series to the amplifying transistor 42 may increase the voltage of the floating diffusion 38 to use lower levels of voltage, as is disclosed, for example, in Japanese Unexamined Patent Application Publication No. 2003-87662.
However, a pixel unit 3 of the 3-TR structure that does not have such a selection transistor cannot employ this technique.
It is more preferable that even a pixel unit 3 of the 4-TR structure that has a selection transistor further decreases power consumption and increases the dynamic range.